The present invention is directed to intermediate frequency (IF) signal processors, in general, and more particularly, to a digital IF processor for sampling and digitizing an IF signal to generate digital data samples thereof at a sampling rate that produces consecutive samples separated in phase by a substantially fixed phase angle 2xcfx80/n, where n is an integer greater than zero, and for processing such data samples digitally to generate digital data samples of in-phase (I), quadrature (Q) and log video (log V) components thereof, the digital IF processor preferably for use in an avionic system for detecting and decoding transponder reply signals from received radio frequency (RF) signals.
Avionic Systems are sometimes applied to the receiving and processing of radio frequency (RF) signals to establish certain information, like the range and bearing of the signal source and the signal information content, for example, which may provide guidance in the navigation of the aircraft. For example, an avionics system for warning of potential air-to-air collisions receives and processes RF signals transmitted from transponders of other aircraft. The operation of such avionic systems, generally referred to as traffic control and collision avoidance systems or TCAS, have been standardized by the Federal Aviation Administration (FAA). In such TCAS systems, the transponders of aircraft are interrogated from ground based radars or other aircraft with request for information signals at 1030 MHz. The transponders reply with signals at 1090 MHz which contain the requested information. Aircraft in the vicinity of the responding aircraft are equipped with avionics to receive and process the RF reply signals to determine range, bearing and altitude information for each responding aircraft. With this information, the avionic system of the receiving aircraft may determine whether or not the responding aircraft is a threat to air-to-air collision therewith and provide a warning thereof.
An exemplary TCAS used in present aircraft is shown in the block diagram schematic of FIG. 1. Generally, these systems include an omni-directional antenna 10 mounted on top of the aircraft for receiving transponder reply signals at 1090 MHz from other aircraft. The antenna 10 may be configured to generate xcexa3 and xcex94 signal components of the reply signals which are supplied to a receiver of the avionics. Typically, the receiver which consists of analog circuitry comprises an RF section 12 for demodulating the RF xcexa3 and xcex94 signals to IF xcexa3 and xcex94 signals, denoted as xcexa3xe2x80x2 and xcex94xe2x80x2 respectively; and an IF section 14 for further demodulating the xcexa3xe2x80x2 and xcex94xe2x80x2 signals to lower IF or baseband signals, denoted as xcexa3xe2x80x3 and xcex94xe2x80x3, respectively. The IF section 14 may also produce a log V signal component. Further included in the avionics is a phase comparator circuit 16 which processes the xcexa3xe2x80x3 and xcex94xe2x80x3 signals to produce the I and Q components thereof. One or more analog-to-digital converters (A/D) 18 digitize the I, Q and log V signals at a predetermined sampling rate and the digitized samples of the I, Q and log V signals are temporarily stored in a set of buffers 20 for later processing in a reply digital processor 22. Reference is made to the U.S. Pat. No. 5,387,915, issued Feb. 7, 1995, entitled xe2x80x9cMethod and Apparatus For Detecting and Decoding Transponder Reply Signalsxe2x80x9d, and assigned to the same assignee as the instant application, for a more detailed description of the structure and operation of TCAS I avionics.
Such avionics are always under scrutiny for improvement, like reducing costs, weight, size, production time and adaptability for changing functionality and compensating for noise interference, for example. The present invention of a digital IF processor replaces the current analog circuitry for IF signal processing, denoted as 24 in FIG. 1, and affords the aforementioned improvements thereover.
In accordance with one aspect of the present invention, apparatus for processing a signal of a predetermined intermediate frequency (IF) to generate in-phase (I) and quadrature (Q) components thereof comprises: an analog-to digital converter circuit for sampling and digitizing the IF signal to generate digitized data samples thereof at a sampling rate that produces consecutive digitized data samples that are separated in phase by a substantially fixed phase angle 2xcfx80/n, where n is an integer greater than zero; first digital circuitry coupled to the analog-to digital converter circuit for demodulating the digitized data samples by multiplying every n consecutive digitized data samples with n respectively corresponding digital reference samples; and second digital circuitry coupled to the first digital circuitry for combining selected ones of the demodulated samples based on the substantially fixed phase angle to generate digital data samples of the I and Q components of the IF signal. The apparatus may include third digital circuitry coupled to the second circuitry for generating digital data samples of a log video component of the IF signal from the digital data samples of the I and Q components.
In accordance with another aspect of the present invention, a digital intermediate frequency (IF) processor for processing IF sum (xcexa3) and delta (xcex94) signals to generate in-phase (I) and quadrature (Q) components of each of the xcexa3 and xcex94 signals comprises: a first analog-to digital converter circuit for sampling and digitizing the IF xcexa3 signal to generate digitized data samples thereof at a sampling rate that produces consecutive digitized data samples of the IF xcexa3 signal that are separated in phase by a substantially fixed phase angle 2xcfx80/n, where n is an integer greater than zero; a second analog-to digital converter circuit for sampling and digitizing the IF xcex94 signal to generate digitized data samples thereof at the sampling rate to produce consecutive digitized data samples of the IF xcex94 signal that are separated in phase by the substantially fixed phase angle; a first digital IF channel coupled to the first analog-to digital converter circuit for processing the digitized data samples of the IF xcexa3 signal to generate digitized data samples of the I and Q components thereof, a second digital IF channel coupled to the second analog-to digital converter circuit for processing the digitized data samples of the IF xcex94 signal to generate digitized data samples of the I and Q components thereof, and wherein each of the I and Q digital IF channels including: first digital circuitry coupled to the corresponding analog-to digital converter circuit for demodulating the digitized data samples by multiplying every n consecutive digitized data samples with n respectively corresponding digital reference samples; and second digital circuitry coupled to the first digital circuitry for combining selected ones of the demodulated samples based on the substantially fixed phase angle to generate digital data samples of said I and Q components of the corresponding IF signal. Each digital IF channel of the processor may include third digital circuitry coupled to the corresponding second circuitry for generating digital data samples of a log video component of the corresponding IF signal from the digital data samples of the I and Q components thereof.
In accordance with yet another aspect of the present invention, an avionic system for detecting and decoding transponder reply signals from received radio frequency (RF) signals comprises: an antenna for receiving the RF signals and configured to produce sum (xcexa3) and delta (xcex94) component signals thereof; an RF receiver circuit for demodulating the RF xcexa3 and xcex94 component signals into intermediate frequency (IF) xcexa3 and xcex94 component signals, respectively; a first analog-to digital converter circuit for sampling and digitizing the IF xcexa3 signal to generate digitized data samples thereof at a sampling rate that produces consecutive digitized data samples of the IF xcexa3 signal that are separated in phase by a substantially fixed phase angle 2xcfx80/n, where n is an integer greater than zero; a second analog-to digital converter circuit for sampling and digitizing the IF xcex94 signal to generate digitized data samples thereof at the sampling rate to produce consecutive digitized data samples of the IF xcex94 signal that are separated in phase by the substantially fixed phase angle; a first digital IF channel coupled to the first analog-to digital converter circuit for processing the digitized data samples of the IF xcexa3 signal to generate digitized data samples of the in-phase (I), quadrature (Q) and log video (log V) components thereof; a second digital IF channel coupled to the second analog-to digital converter circuit for processing the digitized data samples of the IF xcex94 signal to generate digitized data samples of the I, Q and log V components thereof; and a reply processor for processing the digitized data samples of the I, Q and log V components of each of the IF xcexa3 and xcex94 signals to detect and decode transponder reply signals.